Issues of Scale in Semiconductors

8/2/02


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Table of Contents

Issues of Scale in Semiconductors

Growth of the Si industry

Semiconductors: Sutton’s Law of R&D

Some industry issues

Some scaling challenges are fiscal...

Scaling the transistor

Historical scaling

Scaling the interconnect

Voltage scaling

Reductions in power consumption

2001 ITRS: future scaling

The “SIA Roadblock” in CMOS

The materials in the Red Brick Wall

The New “New Materials Review Board”

CMOS beyond the Wall

The oxide: #1 technology challenge

“Doomsday” deferred

Ultimate limit to insulating layer

Nitride distributions in SiON

Beyond SiO2: High-k dielectrics innocent (until …)

The interface challenge

Doping control: TEM for point defect clusters

Doping control requires control of interfacial phases

Interconnect materials

Beyond core CMOS: integrated RF modules, SOC, SIP

Performance modules in CMOS core

The next generation: integrating the system

Materials challenges for CMOS beyond the wall

Beyond Silicon

Improvements in fibre capacity

Optical systems: Heterogeneous integration

Improved optical packing

Silicon MEMS in Optical Networking

Materials challenges for MEMS

Beyond CMOS, post-2002

Summary

Back-ups

Drivers for the Semiconductor Biz

The fibre-optic implosion

CMOS with Dual Gate Oxides

Measuring oxide thicknesses

Oxide reliability E to 1/E extrapolation

The next generation of waveguide devices?

III-V integration: state of the art

The light-emitting capacitor

Author: ncem3